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1.2 ghz clock distribution ic, 1.6 ghz inputs, dividers, five outputs enhanced product ad9512 - ep rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features two 1.6 ghz, differential clock inputs 5 programmable dividers, 1 to 32, all integers 3 independent 1.2 ghz lvpecl outputs additive output jitter 225 fs rms 2 independent 800 mhz/250 mhz lvds/cmos clock outputs additive output jitter : 275 fs rms serial control port space - saving 48 - lead lfcsp enhanced product fea tures supports defense and aerospace applications (aqec standard) military temperature r ange (?55c to +85c) controlled manufacturing baseline 1 assembly/test site 1 fabrication site enhanced product change notification qualification data available on request applications low jitter, low phase noise clock distribution clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes defense and aerospace applications functional block dia gram figure 1. general description the ad9512 - ep provides a multi - output clock distribution in a design that emphasizes low jitter and low phase noise to maxim ize d ata converter performance. other applications with demanding phase noise and jitter requirements can also benefit from this part. there are five independent clock outputs. three outputs are lvpecl (1.2 ghz), and two are selectable as either lvds (800 mhz ) or cmos (250 mhz) levels. each output has a programmable divider that can be bypassed or set to divide by any integer up to 32. the phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a coarse timing adjustment. the ad9512 - ep is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. the ad9512 - ep is available in a 48 - lead lfcsp and can be operated from a single 3.3 v supply. the temperature range is ?55c to +85c. additional application and technical information can be found in the ad9512 data sheet. note that the delay block element that exists in channel 4 of the ad9512 standard product is not supported in this ad9512 - ep version. sync status sync status sclk sdio sdo csb serial control port function syncb, resetb pdb dsync dsyncb detect sync vref rset AD9512-EP gnd vs clk1 clk1b clk2 clk2b programmable dividers and phase adjust out0 out0b lvpecl /1, /2, /3... /31, /32 out1 out1b lvpecl /1, /2, /3... /31, /32 out2 out2b lvpecl /1, /2, /3... /31, /32 out3 out3b lvds/cmos /1, /2, /3... /31, /32 out4 out4b lvds/cmos /1, /2, /3... /31, /32 10463-001
ad9512- ep enhanced product rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 enhanced product features ............................................................ 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 clock inputs .................................................................................. 3 clock o utputs ............................................................................... 3 timing characteristics ................................................................ 4 clock output phase noise .......................................................... 5 clock output additive time ji tter ............................................. 8 serial control port ..................................................................... 10 function pin ......................................................................... 10 sync status pin .................................................................... 11 power ............................................................................................ 11 absolute maximum ratings ......................................................... 12 the rmal characteristics ............................................................ 12 pin configuration and function descriptions ........................... 13 typical performance characteristics ........................................... 15 outline dimension s ....................................................................... 18 ordering guide .......................................................................... 18 revision history 3 /12 revision 0 : initial version
enhanced product ad9512- ep rev. 0 | page 3 of 20 specifications typical (typ) is given for v s = 3.3 v 5%; t a = 25c, r set = 4.12 k ?, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a (? 55c to +85c) variation. clock inputs table 1 . parameter min typ max un it test conditions/comments clock inputs (clk1, clk2) 1 input frequency 0 1.6 ghz input sensitivity 150 2 mv p -p jitter performance can be improved with higher slew rates (greater swing). input level 2 3 v p -p larger swings turn on the protection diodes and can degrade jitter performance. input common - mode voltage, v cm 1.45 1.6 1.7 v self - biased; enables ac coupling; at full temperature range 1.5 1.6 1.7 v at ?40c to +85c . input common - mode range, v cmr 1.3 1.8 v with 200 mv p - p signal applied; dc - coupled. input sensitivity, single - ended 150 mv p -p clk2 ac - coupled; clk2b ac bypassed to rf ground. input resistance 4.0 4.8 5.6 k self - biased. input capacitance 2 pf 1 clk1 and clk2 are electrically identical; each can be used as either differential or single - ended input. 2 with a 50 termination, this is ?12.5 dbm. 3 with a 50 termination, this is +10 dbm. clock outputs table 2 . parameter min typ max unit test conditions/comments lvpecl clock outputs termination = 50 to v s ? 2 v out0, out1, out2; differential output level 0x3d (0x3e) (0x3f)[ 3:2 ] = 10b output frequency 1200 mhz see figure 10 output high voltage (v oh ) v s ? 1.22 v s ? 0.98 v s ? 0.93 v output low voltage (v ol ) v s ? 2.10 v s ? 1.80 v s ? 1.67 v output differential voltage (v od ) 660 810 965 mv lvds clock outputs termination = 100 differential; default out3, out4; differential output level 0x 40 ( 0x 41 )[ 2:1 ] = 01 b 3.5 ma termination current output frequency 800 mhz see figure 11 differential output voltage (v od ) 250 360 450 mv delta v od 25 mv output offset voltage (v os ) 1.05 1.23 1.375 v at full temperature range 1.125 1.23 1.375 v at ?40c to +85c delta v os 25 mv short - circuit current (i sa , i sb ) 14 24 ma output shorted to gnd cmos clock outputs out3, out4 single - ended measurements; b outputs: inverted, termination open output frequency 250 mhz with 5 pf load each output; see figure 12 output voltage high (v oh ) v s ? 0.1 v @ 1 ma load output voltage low (v ol ) 0.1 v @ 1 ma load
ad9512- ep enhanced product rev. 0 | page 4 of 20 timing characteristi cs table 3 . parameter min typ max unit test conditions/comments lvpecl termination = 50 to v s ? 2 v output level 0x3d ( 0x 3e) ( 0x3f)[ 3:2 ] = 10b output rise time, t rp 130 180 ps 20% to 80%, measured differentially output fall time, t fp 130 180 ps 80% to 20%, measured differentially propagation delay, t pecl , clk -to - lvpecl out 1 divide = bypass 320 490 635 ps at full temperature range 335 490 635 ps at ?40c to +85c divide = 2 to 32 360 545 695 ps at full temperature range 375 545 695 ps at ?40c to +85c variation with temperature 0.5 ps/c output skew, lvpecl outputs out1 to out0 on same part, t skp 2 70 100 140 ps out1 to out2 on same part, t skp 2 15 45 80 ps out0 to out2 on same part, t skp 2 45 65 90 ps all lvpecl out across multiple parts, t skp_ab 3 275 ps same lvpecl out across multiple parts, t skp_ab 3 130 ps lvds termination = 100 differential output level 0x 40 ( 0x41 ) [ 2:1 ] = 01b 3.5 ma termination current output rise time, t rl 200 350 ps 20% to 80%, measured differentially output fall time, t fl 210 350 ps 80% to 20%, measured differentially propagation delay, t lvds , clk -to - lvds out 1 out3 to out4 divide = bypass 0.97 1.33 1.59 ns at full temperature range 0.99 1.33 1.59 ns at ?40c to +85c divide = 2 to 32 1.02 1.38 1.64 ns at full temperature range 1.04 1.38 1.64 ns at ?40c to +85c variation with temperature 0.9 ps/c output skew, lvds outputs out3 to out4 on same part, t skv 2 ?85 +270 ps all lvds outs across multiple parts, t skv_ab 3 450 ps same lvds out across multiple parts, t skv_ab 3 325 ps cmos b outputs are inverted; termination = open output rise time, t rc 681 865 ps 20% to 80%; c load = 3 pf output fall time, t fc 646 992 ps 80% to 20%; c load = 3 pf propagation delay, t cmos , clk -to - cmos out 1 divide = bypass 1.0 1.39 1.71 ns at full temperature range 1.02 1.39 1.71 ns at ?40c to +85c divide = 2 to 32 1.05 1.44 1.76 ns at full temperature range 1.07 1.44 1.76 ns at ?40c to +85c variation with temperature 1 ps/c output skew, cmos outputs out3 to out4 on same part, t skc 2 ?140 +145 +300 ps all cmos out across multiple parts, t skc_ab 3 650 ps same cmos out across multiple parts, t skc_ab 3 500 ps lvpecl -to - lvds out everything the same; different logic type output skew, t skp_v 0.73 0.92 1.14 ns lvpecl to lvds on same part lvpecl -to - cmos out everything the same; different logic type output skew, t skp_c 0.87 1.14 1.43 ns lvpecl to cmos on same part
enhanced product ad9512- ep rev. 0 | page 5 of 20 parameter min typ max unit test conditions/comments lvds -to - cmos out everything the same; different logic type output skew, t skv_c 158 353 506 ps lvds to cmos on same part 1 the measurements are for clk1. for clk2, add approximately 25 ps. 2 this is the difference between any two similar delay paths within a single device operating at the same voltage and temperatu re. 3 this is the difference between any two similar delay paths across multiple devices operating at the same voltage an d temperature. clock output phase noise table 4 . parameter min typ max unit test conditions/comments clk1 - to - lvpecl additive phase noise clk1 = 622.08 mhz, out = 622.08 mhz input slew rate > 1 v/ns divide ratio = 1 @ 10 hz offset ?125 dbc/hz @ 100 hz offset ?132 dbc/hz @ 1 khz offset ?140 dbc/hz @ 10 khz offset ?148 dbc/hz @ 100 khz offset ?153 dbc/hz >1 mhz offset ?154 dbc/hz clk1 = 622.08 mhz, out = 155.52 mhz divide ratio = 4 @ 10 hz offset ?128 dbc/hz @ 100 hz offset ?140 dbc/hz @ 1 khz offset ?148 dbc/hz @ 10 khz offset ?155 dbc/hz @ 100 khz offset ?161 dbc/hz >1 mhz offset ?161 dbc/hz clk1 = 622.08 mhz, out = 38.88 mhz divide ratio = 16 @ 10 hz offset ?135 dbc/hz @ 100 hz offset ?145 dbc/hz @ 1 khz offset ?158 dbc/hz @ 10 khz offset ?165 dbc/hz @ 100 khz offset ?165 dbc/hz >1 mhz offset ?166 dbc/hz clk1 = 491.52 mhz, out = 61.44 mhz divide ratio = 8 @ 10 hz offset ?131 dbc/hz @ 100 hz offset ?142 dbc/hz @ 1 khz offset ?153 dbc/hz @ 10 khz offset ?160 dbc/hz @ 100 khz offset ?165 dbc/hz >1 mhz offset ?165 dbc/hz clk1 = 491.52 mhz, out = 245.76 mhz divide ratio = 2 @ 10 hz offset ?125 dbc/hz @ 100 hz offset ?132 dbc/hz @ 1 khz offset ?140 dbc/hz @ 10 khz offset ?151 dbc/hz @ 100 khz offset ?157 dbc/hz >1 mhz offset ?158 dbc/hz
ad9512- ep enhanced product rev. 0 | page 6 of 20 parameter min typ max unit test conditions/comments clk1 = 245.76 mhz, out = 61.44 mhz divide ratio = 4 @ 10 hz offset ?138 dbc/hz @ 100 hz offset ?144 dbc/hz @ 1 khz offset ?154 dbc/hz @ 10 khz offset ?163 dbc/hz @ 100 khz offset ?164 dbc/hz >1 mhz offset ?165 dbc/hz clk1 - to - lvds additive phase noise clk1 = 622.08 mhz, out = 622.08 mhz divide ratio = 1 @ 10 hz offset ?100 dbc/hz @ 100 hz offset ?110 dbc/hz @ 1 khz offset ?118 dbc/hz @ 10 khz offset ?129 dbc/hz @ 100 khz offset ?135 dbc/hz @ 1 mhz offset ?140 dbc/hz >10 mhz offset ?148 dbc/hz clk1 = 622.08 mhz, out = 155.52 mhz divide ratio = 4 @ 10 hz offset ?112 dbc/hz @ 100 hz offset ?122 dbc/hz @ 1 khz offset ?132 dbc/hz @ 10 khz offset ?142 dbc/hz @ 100 khz offset ?148 dbc/hz @ 1 mhz offset ?152 dbc/hz >10 mhz offset ?155 dbc/hz clk1 = 491.52 mhz, out = 245.76 mhz divide ratio = 2 @ 10 hz offset ?108 dbc/hz @ 100 hz offset ?118 dbc/hz @ 1 khz offset ?128 dbc/hz @ 10 khz offset ?138 dbc/hz @ 100 khz offset ?145 dbc/hz @ 1 mhz offset ?148 dbc/hz >10 mhz offset ?154 dbc/hz clk1 = 491.52 mhz, out = 122.88 mhz divide ratio = 4 @ 10 hz offset ?118 dbc/hz @ 100 hz offset ?129 dbc/hz @ 1 khz offset ?136 dbc/hz @ 10 khz offset ?147 dbc/hz @ 100 khz offset ?153 dbc/hz @ 1 mhz offset ?156 dbc/hz >10 mhz offset ?158 dbc/hz clk1 = 245.76 mhz, out = 245.76 mhz divide ratio = 1 @ 10 hz offset ?108 dbc/hz @ 100 hz offset ?118 dbc/hz @ 1 khz offset ?128 dbc/hz @ 10 khz offset ?138 dbc/hz @ 100 khz offset ?145 dbc/hz @ 1 mhz offset ?148 dbc/hz >10 mhz offset ?155 dbc/hz
enhanced product ad9512- ep rev. 0 | page 7 of 20 parameter min typ max unit test conditions/comments clk1 = 245.76 mhz, out = 122.88 mhz divide ratio = 2 @ 10 hz offset ?118 dbc/hz @ 100 hz offset ?127 dbc/hz @ 1 khz offset ?137 dbc/hz @ 10 khz offset ?147 dbc/hz @ 100 khz offset ?154 dbc/hz @ 1 mhz offset ?156 dbc/hz >10 mhz offset ?158 dbc/hz clk1 - to - cmos additive phase noise clk1 = 245.76 mhz, out = 245.76 mhz divide ratio = 1 @ 10 hz offset ?110 dbc/hz @ 100 hz offset ?121 dbc/hz @ 1 khz offset ?130 dbc/hz @ 10 khz offset ?140 dbc/hz @ 100 khz offset ?145 dbc/hz @ 1 mhz offset ?149 dbc/hz > 10 mhz offset ?156 dbc/hz clk1 = 245.76 mhz, out = 61.44 mhz divide ratio = 4 @ 10 hz offset ?122 dbc/hz @ 100 hz offset ?132 dbc/hz @ 1 khz offset ?143 dbc/hz @ 10 khz offset ?152 dbc/hz @ 100 khz offset ?158 dbc/hz @ 1 mhz offset ?160 dbc/hz >10 mhz offset ?162 dbc/hz clk1 = 78.6432 mhz, out = 78.6432 mhz divide ratio = 1 @ 10 hz offset ?122 dbc/hz @ 100 hz offset ?132 dbc/hz @ 1 khz offset ?140 dbc/hz @ 10 khz offset ?150 dbc/hz @ 100 khz offset ?155 dbc/hz @ 1 mhz offset ?158 dbc/hz >10 mhz offset ?160 dbc/hz clk1 = 78.6432 mhz, out = 39.3216 mhz divide ratio = 2 @ 10 hz offset ?128 dbc/hz @ 100 hz offset ?136 dbc/hz @ 1 khz offset ?146 dbc/hz @ 10 khz offset ?155 dbc/hz @ 100 khz offset ?161 dbc/hz >1 mhz offset ?162 dbc/hz
ad9512- ep enhanced product rev. 0 | page 8 of 20 clock output additiv e time jitter table 5 . parameter min typ max unit test conditions/comments lvpecl output additive time jitter clk1 = 622.08 mhz , 40 fs rms bw = 12 khz to 20 mhz (oc -12) any lvpecl (out0 to out2) = 622.08 mhz, divide ratio = 1 clk1 = 622.08 mhz 55 fs rms bw = 12 khz to 20 mhz (oc -3) any lvpecl (out0 to out2) = 155.52 mhz divide ratio = 4 clk1 = 400 mhz 215 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz any lvpecl (out0 to out2) = 100 mhz divide ratio = 4 clk1 = 400 mhz 215 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz any lvpecl (out0 to out2) = 100 mhz divide ratio = 4 other lvpecl = 100 mhz interferer(s) both lvds (out3, out4) = 100 mhz interferer(s) clk1 = 400 mhz 222 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz any lvpecl (out0 to out2) = 100 mhz divide ratio = 4 other lvpecl = 50 mhz interferer(s) both lvds (out3, out4) = 50 mhz interferer(s) clk1 = 400 mhz 225 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz any lvpecl (out0 to out2) = 100 mhz divide ratio = 4 other lvpecl = 50 mhz interferer(s) both cmos (out3, out4) = 50 mhz (b outputs off ) interferer(s) clk1 = 400 mhz 225 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz any lvpecl (out0 to out2) = 100 mhz divide ratio = 4 other lvpecl = 50 mhz interferer(s) both cmos (out3, out4) = 50 mhz (b outputs on) interferer(s) lvds output additive time jitter clk1 = 400 mhz 264 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out3) = 100 mhz divide ratio = 4 clk1 = 400 mhz 319 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out4) = 100 mhz divide ratio = 4 clk1 = 400 mhz 395 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out3) = 100 mhz divide ratio = 4 lvds (out4) = 50 mhz interferer(s) all lvpecl = 50 mhz interferer(s)
enhanced product ad9512- ep rev. 0 | page 9 of 20 parameter min typ max unit test conditions/comments clk1 = 400 mhz 395 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out4) = 100 mhz divide ratio = 4 lvds (out3) = 50 mhz interferer(s) all lvpecl = 50 mhz interferer(s) clk1 = 400 mhz 367 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out3) = 100 mhz divide ratio = 4 cmos (out4) = 50 mhz (b outputs off ) interferer(s) all lvpecl = 50 mhz interferer(s) clk1 = 400 mhz 367 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out4) = 100 mhz divide ratio = 4 cmos (out3) = 50 mhz (b outputs off ) interferer(s) all lvpecl = 50 mhz interferer(s) clk1 = 400 mhz 548 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out3) = 100 mhz divide ratio = 4 cmos (out4) = 50 mhz (b outputs on) interferer(s) all lvpecl = 50 mhz interferer(s) clk1 = 400 mhz 548 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz lvds (out4) = 100 mhz divide ratio = 4 cmos (out3) = 50 mhz (b outputs on) interferer(s) all lvpecl = 50 mhz interferer(s) cmos output additive time jitter clk1 = 400 mhz 275 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz both cmos (out3, out4) = 100 mhz (b output on) divide ratio = 4 clk1 = 400 mhz 400 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz cmos (out3) = 100 mhz (b output on) divide ratio = 4 all lvpecl = 50 mhz interferer(s) lvds (out4) = 50 mhz interferer(s) clk1 = 400 mhz 374 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz cmos (out3) = 100 mhz (b output on) divide ratio = 4 all lvpecl = 50 mhz interferer(s) cmos (out4) = 50 mhz (b output off ) interferer(s) clk1 = 400 mhz 555 fs rms calculated from snr of adc method; f c = 100 mhz with a in = 170 mhz cmos (out3) = 100 mhz (b output on) divide ratio = 4 all lvpecl = 50 mhz interferer(s) cmos (out4) = 50 mhz (b output on) interferer(s)
ad9512- ep enhanced product rev. 0 | page 10 of 20 serial control port table 6 . parameter min typ max unit test conditions/comments csb, sclk (inputs) csb and sclk have 30 k internal pull - down resistors input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 110 a input logic 0 current 1 a input capacitance 2 pf sdio (when input) input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 10 na input logic 0 current 10 na input capacitance 2 pf sdio, sdo (outputs) output logic 1 voltage 2.7 v output logic 0 voltage 0.4 v timing clock rate (sclk, 1/t sclk ) 25 mhz pulse width high, t pwh 16 ns pulse width low, t pwl 16 ns sdio to sclk setup, t ds 2 ns sclk to sdio hold, t dh 1 ns sclk to valid sdio and sdo, t dv 6 ns csb to sclk setup and hold, t s , t h 2 ns csb minimum pulse width high, t pwh 3 ns function pin table 7 . parameter min typ max unit test conditions/comments input characteristics the function pin has a 30 k internal pull - down resistor. this pin should normally be held high. do not let input float . logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 110 a logic 0 current 1 a capacitance 2 pf reset timing pulse width low 50 ns sync timing pulse width low 1.5 high speed clock cycles high speed clock is clk1 or clk2, whichever is being used for distribution.
enhanced product ad9512- ep rev. 0 | page 11 of 20 sync status pin table 8 . parameter min typ max unit test conditions/comments output characteristics output voltage high (v oh ) 2.7 v output voltage low (v ol ) 0.4 v power table 9 . parameter min typ max unit test conditions/comments power - up default mode power dissipation 550 600 mw power - up default state; does not include power dissipated in output load resistors. no clock. power dissipation 800 mw all outputs on. three lvpecl outputs @ 800 mhz, two cmos out @ 62 mhz ( 5 pf load). does not include power dissipated in external resistors. 850 mw all outputs on. three lvpecl outputs @ 800 mhz, two cmos out @ 125 mhz ( 5 pf load). does not include power dissipated in external resistors. full sleep power - down 35 60 mw maximum sleep is entered by setting 0x 0a [ 1:0 ] = 01b and 0x 58 [4] = 1b. this powers off all band gap references. does not include power dissipated in terminations. power - down (pdb) 60 80 mw set function pin for pdb operation by setting 0x 58[ 6:5 ] = 11 b. pull pdb low. does not include power dissipated in terminations. power delta clk1, clk2 power - down 10 15 25 mw divider, div 2 to 32 to bypass 23 27 33 mw for each divider. lvpecl output power - down (pd2, pd3) 50 65 75 mw for each output. does not include dissipation in termination (pd2 only). lvds output power - down 80 92 110 mw for each output. cmos output power - down (static) 56 70 85 mw for each output. static (no clock). cmos output power - down (dynamic) 115 150 190 mw for each cmos output, single - ended. clocking at 62 mhz with 5 pf load. cmos output power - down (dynamic) 125 165 210 mw for each cmos output, single - ended. clocking at 125 mhz with 5 pf load.
ad9512- ep enhanced product rev. 0 | page 12 of 20 absolute maximum rat ings table 10. parameter with respect to rating vs gnd ?0.3 v to +3.6 v dsync/dsyncb gnd ?0.3 v to v s + 0.3 v rset gnd ?0.3 v to v s + 0.3 v clk1, clk1b, clk2, clk2b gnd ?0.3 v to v s + 0.3 v clk1 clk1b ?1.2 v to +1.2 v clk2 clk2b ?1.2 v to +1.2 v sclk, sdio, sdo, csb gnd ?0.3 v to v s + 0.3 v out0, out1, out2, out3, out4 gnd ?0.3 v to v s + 0.3 v function gnd ?0.3 v to v s + 0.3 v sync status gnd ?0.3 v to v s + 0.3 v junction temperature 150c storage temperature range ?65c to +150c lead temperature (10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. thermal characterist ics table 11 . thermal resistance 1 package type ja unit 48 - lead lfcsp 28.5 c/w 1 thermal impedance measurements were taken on a 4 - layer board in still air, in accordance with eia/jesd51 - 7. esd caution
enhanced product ad9512- ep rev. 0 | page 13 of 20 pin configuration an d function descripti ons figure 2 . pin configuration table 12 . pin function descriptions pin o. nemonic description 1 dsync detect sync. used for multichip synchronization. 2 dsyncb detect sync complement. used for multichip synchronization. 3 , 4 , 6 , 9 , 18, 22, 23, 25 , 28, 29, 32, 33 , 36, 39, 40, 44, 47, 48 vs power supply (3.3 v). 5 dnc do not connect. do not connect to this pin. 7 clk2 clock input. 8 clk2b complementary clock input. used in conjunction with clk2. 10 clk1 clock input. 11 clk1b complementary clock input. used in conjunction with clk1. 12 function multipurpose input. can be programmed as a reset (resetb), sync (syncb), or power - down (pdb) pin. 13 sync status output used to monitor the status of multichip synchronization. 14 sclk serial data clock. 15 sdio serial data i/o. 16 sdo serial data output. 17 csb serial port chip select. 19, 24, 37 , 38, 43, 46 gnd ground. 20 out2b complementary lvpecl output. 21 out2 lvpecl output. 26 out1b complementary lvpecl output. 27 out1 lvpecl output. 30 out4b complementary lvds/inverted cmos output. notes 1. dnc = do not connect to this pin. 2. the exposed paddle on this package is an electrical connection as well as a thermal enhancement. for the device to function properly, the paddle must be attached to ground, gnd. pin 1 indicator 48 47 46 45 44 43 42 41 40 39 38 vs vs gnd rset vs gnd out0 out0b vs vs gnd 1 2 3 4 5 6 7 8 9 10 11 12 dsync dsyncb vs vs dnc vs clk2 clk2b vs clk1 clk1b function vs out3 out3b vs vs out4 out4b vs vs out1 out1b vs 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 sync status sclk sdio sdo csb vs gnd out2b out2 vs vs gnd 37 gnd AD9512-EP top view (not to scale) 10463-002
ad9512- ep enhanced product rev. 0 | page 14 of 20 pin no. mnemonic description 31 out4 lvds/cmos output. 34 out3b complementary lvds/inverted cmos output. 35 out3 lvds/cmos output. 41 out0b complementary lvpecl output. 42 out0 lvpecl output. 45 rset current set resistor to ground. nominal value = 4.12 k. epad exposed pad dle . the exposed pad dle on this package is an electrical connection as well as a thermal enhancement. for the device to function properly, the pad dle must be attached to ground, gnd.
enhanced product ad9512- ep rev. 0 | page 15 of 20 typical performance characteristics figure 3 . power vs. frequency lvpecl, lvds figure 4 . clk1 smith chart (evaluation board) figure 5 . power vs. frequency lvpecl, cmos figure 6 . clk2 smith chart (evaluation board) output frequency (mhz) power (w) 0 800 400 0.3 0.6 0.5 0.4 3 lvpecl (div on) 2 lvds (div on) default ? 3 lvpecl + 2 lvds (div on) 3 lvpecl + 2 lvds (div bypassed) 10463-003 5mhz clk1 (eval board) 3ghz 10463-004 output frequency (mhz) power (w) 0 120 100 80 60 40 20 0.4 0.7 0.6 0.5 3 lvpecl + 2 cmos (div on) 10463-005 5mhz clk2 (eval board) 3ghz 10463-006
ad9512- ep enhanced product rev. 0 | page 16 of 20 figure 7 . lvpecl differential output @ 800 mhz figure 8 . lvds differential output @ 800 mhz figure 9. cmos single - ended output @ 250 mhz with 10 pf load figure 10 . lvpecl differential output swing vs. frequency figure 11 . lvds differential output swing vs. frequency figure 12 . cmos single - ended output swing vs. frequency and load vert 500mv/div horiz 500ps/div 10463-007 vert 100mv/div horiz 500ps/div 10463-008 vert 500mv/div horiz 1ns/div 10463-009 output frequency (mhz) differential swing (v p-p) 100 1600 1100 600 1.2 1.3 1.4 1.5 1.6 1.7 1.8 10463-010 output frequency (mhz) differential swing (mv p-p) 100 900 700 500 300 500 750 700 650 600 550 10463-011 output frequency (mhz) output (v pk ) 0 600 500 400 300 200 100 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2pf 10pf 20pf 10463-012
enhanced product ad9512- ep rev. 0 | page 17 of 20 figure 13 . additive phase noise lvpecl div1, 245.76 mhz distribution section only figure 14 . additive phase noise lvds div1, 245.76 mhz figure 15 . additive phase noise cmos div1, 245.76 mhz figure 16 . additive phase noise lvpecl div1, 622.08 mhz figure 17 . additive phase noise lvds div2, 122.88 mhz figure 18 . additive phase noise cmos div4, 61.44 mhz offset (hz) l(f) (dbc/hz) 10 10m 1m 100k 10k 1k 100 ?170 ?1 10 ?130 ?120 ?140 ?150 ?160 10463-013 offset (hz) l(f) (dbc/hz) 10 10m 1m 100k 10k 1k 100 ?170 ?80 ?90 ?1 10 ?100 ?120 ?130 ?140 ?150 ?160 10463-014 offset (hz) l(f) (dbc/hz) 10 10m 1m 100k 10k 1k 100 ?170 ?100 ?1 10 ?120 ?130 ?140 ?150 ?160 10463-015 offset (hz) l(f) (dbc/hz) 10 10m 1m 100k 10k 1k 100 ?170 ?1 10 ?130 ?120 ?140 ?150 ?160 10463-016 offset (hz) l(f) (dbc/hz) 10 10m 1m 100k 10k 1k 100 ?170 ?80 ?90 ?1 10 ?100 ?120 ?130 ?140 ?150 ?160 10463-017 offset (hz) l(f) (dbc/hz) 10 10m 1m 100k 10k 1k 100 ?170 ?100 ?1 10 ?120 ?130 ?140 ?150 ?160 10463-018
ad9512- ep enhanced product rev. 0 | page 18 of 20 outline dimensions figure 19 . 48 - lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp - 48 - 1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9512ucpz -ep ?55c to +85c 48 - lead lead frame chip scale package [ lfcsp_vq ] cp -48 -1 ad9512ucpz -ep-r7 ?55c to +85c 48 - lead lead frame chip scale package [ lfcsp_vq ] cp -48 -1 1 z = rohs compliant part. pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 080108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet.
enhanced product ad9512- ep rev. 0 | page 19 of 20 notes
ad9512- ep enhanced product rev. 0 | page 20 of 20 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10463 - 0 - 3/12(0)

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